Metallic contamination poses costly threats to the microelectronics
industry. Conventional measurement techniques cannot be applied
on-line. Looking for a new approach, a consortium of three organisations
assessed and calibrated three novel methods which indirectly measure
contamination via carrier lifetime. All three techniques performed
well and the project resulted in a proposed standard for the on-line
measurement of metallic contamination in silicon wafers.
As we move into the Information Age, new products and developments will demand improvements within microelectronics technology, especially within the area of Ultra Large Scale Integration (ULSI) of integrated circuits which is packing more transistors on to chips than ever before. Silicon contamination is a major problem and if the industry is to move forward, it will need higher purity starting materials and better techniques to measure and monitor contamination during the integrated circuit fabrication process, which can comprise hundreds of steps.
When it comes to wafer contamination the main culprits are metals. These include sodium and potassium, as well as heavy metals like iron, copper, nickel and chromium. These metals lower performance, reliability and device yield - the number of "good" devices from one silicon wafer divided by the number of total devices on the wafer. They achieve this by changing the conduction properties of the silicon semiconductor. For example, in transistors, alkali metals like sodium introduce mobile charge into the thin layer of oxide which acts as the gate dielectric in the transistor. The oxide's insulating properties are soon nullified. Transition metals, on the other hand, act as traps for electrons, removing them from circulation as charge carriers for a relatively long time. Metallic concentrations of less than one part per billion can render the semiconductor wafer useless for making devices.
The costs of contamination are immense. "What can happen," says Patrick Kelly of the Irish National Microelectronics Research Centre (NMRC), "is that an integrated circuit fabrication facility, known in the trade as a fab, has a yield excursion in its process. This means that an entirely or substantially failed batch of wafers comes out of its facility. This can cause the entire line to be shut down at worst, until the problem is found. We have seen examples of costs of US$150,000 associated with a single yield excursion."
Such costly disasters can be avoided by monitoring every step of the process. This could mean running a test wafer through an oxidation furnace with every batch and then promptly measuring the electrical effects of contamination. That way, you notice the contamination problem long before it gets to a critical stage.
On-line monitoring simply was not possible with the traditional chemical techniques used to measure contamination. Here, water solutions of the metallic contaminants would be extracted by a chemical process from the wafer and measured by spectroscopic methods which takes too long, costs too much and is not practical on-line.
Chipping in to research
Under the Standards, Measurements and Testing programme, the NMRC - one of Europe's leading centres in microelectronics research, MEMC - a silicon wafer manufacturer, and GeMeTeC - an instrumentation manufacturer and analytical services laboratory, came together to develop a comprehensive On-line Measurement Methodology for the determination of extremely low
levels of Contamination of Silicon, using novel techniques. These techniques, called Surface Charge Analysis (SCA), Microwave-photoconductivity decay (micro-PCD) and Electrolytic Metal Analysis (Elymat), each measure the electrical effects of contamination rather than concentration. "How they work would require a detailed physics explanation - or three of them!" explains Patrick Kelly, the OMMCOS project coordinator. "Their common feature is an ability to measure the lifetime of the minority charge carriers in the silicon wafer. This parameter has a well-known relationship to the concentration of iron distributed through the silicon wafer bulk." In short, they are simpler and can be operated on-line in a fab. Some have the potential to be non-destructive, meaning that you can make circuits and test the wafer in certain cases.
Each of the partners assessed and calibrated a different measurement technique, using specially designed sample materials that incorporate the various contaminants affecting final device production. The team identified these by surveying the microelectronics community. Their results indicate that all three techniques are sensitive enough to measure less than one part per billion metallic contamination concentration. The SCA - surface charge analysis - work gave particularly interesting results because a relationship between the quantity known as the SCA lifetime and the conventionally measured minority carrier lifetime was revealed.
Setting the standard
The project did not only set out to develop these measurement methods. The ultimate aim is to develop a European standard for on-line monitoring of silicon contamination. The partners will submit their results to the relevant standards body, CENELEC, which has a working group responsible for devising a standard.
With the developments in on-line measurement methods being proposed as a written standard, OMMCOS project results will certainly affect the microelectronics industry, although it will take two to three years to develop the standard. "Without funding from the Standards, Measurements and Testing programme, the three partners would not have been able to afford the full costs of the study, nor would we have had access to the facilities for making deliberately contaminated test wafers,"
concludes Dr Kelly.