TOPIC : European high-performance, trustable (re)configurable system-on-a-chip or system-in-package for defence applications
|Publication date:||15 March 2018|
|Types of action:||PPPA-PADR-RA Preparatory Action on Defence Research – Research Action|
|DeadlineModel: Opening date:||single-stage 15 March 2018||Deadline:||28 June 2018 17:00:00|
|Time Zone : (Brussels time)|
07 May 2018 17:18
We have updated the document with the topic related frequently asked questions - see the topic conditions section below.
25 April 2018 16:45
The presentations of the PADR 2018 Info & Brokerage Day of 12 April are now published on the EDA website.
Please note that the deadline to submit questions about the call to PreparatoryAction@eda.europa.eu is 21 June EOB.
11 April 2018 17:30
We have published the topic related frequently asked questions - see the topic conditions section below.
Topic DescriptionSpecific Challenge:
High-resolution and high-speed data acquisition impose ever stronger real-time requirements on data processing components on which an increasing number of defence applications critically depend upon in areas such as communications, electronic warfare, encryption, digital imaging, as well as radar and secure positioning, navigation and timing (PNT). General purpose processors show too low performance levels for critical processes in such defence applications.
Hence the need for defence-specific hard- and software approaches. These functionalities can be embedded in high-density electronic components that can be configured or even reconfigured (such as Field Programmable Gate Arrays amongst others), are combined on a single System-on-Chip (SoC) or distributed over a Multi-Chip-Module (or other System-in-Package (SiP) solutions). The selection of the preferred technological solution should strike a balance between the requirements of the defence application(s) (in terms of, e.g., bandwidth, latency, flexibility, cryptologic restrictions, spatial requirements, power consumption), and economic drivers (such as the number of units expected to be produced, time to enter into service, the upfront costs (e.g., to non-recurring engineering), maintenance needs).
Performant (re)configurable SoC/SiPs are commercially available for a wide variety of applications in civil domains including medical and consumer electronics, automotive, and high performance computing. Using (re)configurable SoC/SiPs in (aero)space and defence applications adds stringent requirements for operation under harsh conditions. Moreover, military users need to be sure that these components can be trusted for use, e.g., in security systems, communication equipment and encryption algorithms available without restrictions.
For these technologies which are critical for a number of defence applications, the EU is currently fully dependent on suppliers established in non-EU countries, which implies risks of supply chains and vulnerabilities in terms of security. Furthermore, a number of regulations of non-EU nations can impose end-user restrictions on the use of the technologies (e.g., the US International Traffic in Arms and Export Administration Regulations (ITAR and EAR)). Setting up a EU-based supply chain for high-performance, trustable (re)configurable SoC/SiP for defence applications would contribute to remove these important limitations, as well as creating business opportunities in other highly demanding sectors beyond the defence sector.Scope:
Proposals should design and validate a SoC/SiP and as such make a substantial contribution towards the development and manufacturing of European high-performance, trustable (re)configurable SoC/SiP suitable for multiple defence applications.
Design considerations and engineering decisions on the architecture of the SoC/SiP should thereby be driven by the state-of-the-art requirements of the selected defence applications. In particular long-term operation under harsh conditions, such as severe temperature variations, intense vibrations, and elevated radiation levels, as well as specific power requirements, should be adequately taken into account.
The design has to take into account that the manufacturing needs of the SoC/SiP should match the production capabilities of ideally more than one trustable fab or foundry established in the EU. In parallel to the proposed advances at the hardware level, advancing innovative development and debugging tools should be explored. They should enable to work at a high level of abstraction to design, simulate, integrate, synthesise, and test systems on the target device. Enhanced performance and shorter development times should be demonstrated by removing the debugging barrier between the processor and the (re)configurable component of the SoC/SiP.
Proposals should pay particular attention to security protection of the proposed hardware and software solutions.
The SoC/SiP architecture should be protected from intrusion or attacks, e.g., by secure boot mechanisms, embedding encryption engines, anti-tamper (which can be based on emerging technologies such as Physical Unclonable Functions (PUF)), anti-reverse engineering techniques and TEMPEST protection ideally allowing unclassified handling of information. The design and manufacturing process should be highly controlled to exclude that weaknesses, back doors or Trojan horses are implemented in the hardware and software components and systems. Flexible packaging options should be offered for the SoC/SiP device. When requested known good dies (KGD) should be supplied as well. The proposed security measures should be in line with the recommendations issued by the relevant national crypto approval authorities (CAA) of at least two Member States or Norway to handle information up to the national equivalents of SECRET UE/EU SECRET provided under Council Decision 2013/488/EU  and Commission Decision (EU, Euratom) 2015/444.
Hardware and software products developed in the context of this topic should not be subject to non-EU export control regulations.
Proposals should include a size, weight, power and cost (SWaP-C) analysis to support the proposed (re)configurable SoC/SiP technology as well as a high-level description of the key performance indicators (KPIs) for state-of-the-art performance of the envisaged functionalities, and the methodologies on how to measure them. A report with a detailed description of these KPIs and methodologies should be delivered within 6 months after the start of the project.
In order to meet future capacity and performance requirements, the components should be implemented in a technology node (minimum transistor feature size) of 28 nm or smaller.
If the proposed architecture includes a FPGA, the SoC/SiP need to include at least the following features:
- 200k Look-Up Table (LUTs);
- Internal non-volatile memory;
- Digital Signal Processing hard-macros;
- Flexible interconnections between the DSP processing core, general processing cores and on- and off chip bridges and interfaces;
- Encryption module and anti-tamper and TEMPEST protection (as set out above);
- At least 10 Gb/s high-speed links / interfaces.
Deviations from the set of features listed above should be duly justified in view of the multiple defence applications envisaged.
The potential of the proposed solutions, in particular in the security and space domain, should be thoroughly explored.
When relevant, results publicly available from EDA and NATO activities and studies should be taken into account for the proposed work. The activities included in the proposals should clearly differentiate from or go beyond work already covered under relevant themes of the EU Research and Innovation Framework Programmes.
The implementation of this topic is intended to start at TRL 2 to 3 and target TRL 5.
The Commission considers that proposal requesting a contribution from the Union between EUR 8 000 000 and 12 000 000 would allow this specific challenge to be addressed appropriately. Nonetheless, this does not preclude submission and selection of proposals requesting other amounts.
No more than one action will be funded.Expected Impact:
- Convincing demonstration of the potential of EU-funded research in support of EU critical defence technologies, in particular in the domain of (re)configurable SoC/SiPs;
- Ensure secure and autonomous availability of high performance and trustable (re)configurable SoC/SiPs to military end-users;
- Contribute to strengthening the European microelectronics industry and help improve its global position through the implementation of innovative technologies along a new European manufacturing value chain;
- Improved competitiveness of the end-user industry in and beyond the defence sector.
(Re)configurable components include but are not limited to (re)programmable components.
Work on Application Specific Integrated Circuits (ASICs) is outside the scope of this call.
Council Decision 2013/488/EU of 23 September 2013 on the security rules for protecting EU classified information (OJ L274, 15.10.2013, p. 1).
Commission Decision (EU, Euratom) 2015/444 of 13 March 2015 on the security rules for protecting EU classified information, OJ L72, 17.3.2015, p. 53.
Applicants are invited to consult the Work programme 2018-2020 "5.iii. Leadership in Enabling and Industrial Technologies – Space", and in particular the technical guidance documents listed in the Work programme.
Topic conditions and documents
1. Eligible countries: described in General Annex A of Call document 2018.
2. Eligibility and admissibility conditions: described in General Annexes B and C of Call Document 2018.
(a) at least three legal entities shall participate in an action;
(b) these three legal entities shall each be established in a different EU Member State or Norway;
(c) the legal entities referred to in point (b) shall be independent of each other within the meaning described in General Annex C.
Proposal page limits and layout: 70 pages for sections 1-3 of part B (technical part) of the proposal template.
Award criteria, scoring, thresholds and process are described in General Annex F of Call Document 2018.
4. Indicative timetable for evaluation and grant agreement:
Outcome of the evaluation: maximum 6 months from the final date for submission.
Signature of grant agreements: maximum 3 months from the date of informing successful applicants.
5. Proposal templates, guidance and model grant agreements (MGA):
In the ethics issues table of the template, questions 8 and 9 are not applicable to the Preparatory Action on Defence Research (PADR). Please reply “NO” to both questions. Please also note that the Ethics Self-Assessment Guide which you can access from the table is NOT applicable to PADR.
2018 Calls for Proposals and General Annexes
Guide for Applicants
Multi-beneficiary Model Grant Agreement
The budget of this topic is up to EUR 12,000,000.
Legal entities, other than those exempted (like public bodies), applying for an EU financial contribution equal or above EUR 60 000 are also subject to a verification of their financial capacity. For the complete information, please see pages 8-10 in the Guide for Applicants.
Agreement on background: Consortium members should identify in the proposal the background for the project, setting out in detail all existing restrictions on the use or export of this background.
The successful consortia involved in PADR Research Actions will have to submit a Special Report using the template provided in Annex I to the Call Document. As stated in Article 19 of the PADR MGA, these reports have to be submitted 30 days after the deadline for periodic reports and shall be made available to the Member States and Norway.
Members of consortium are required to conclude a consortium agreement, in principle prior to the signature of the grant agreement.
- Topic related Q&A en
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|Type of Action||Preparatory Action on Defence Research - Research Action [PPPA-PADR-RA]|
|Topic||European high-performance, trustable (re)configurable system-on-a-chip or system-in-package for defence applications - PADR-EDT-02-2018|
|Guidance on proposal submission:||H2020 online manual|
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