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   Infocentre

Last Update: 12-02-2014  
Related category(ies):
Information society  |  Industrial research  |  Nanotechnology

 

Countries involved in the project described in the article:
France  |  Ireland  |  Netherlands  |  Romania  |  Serbia
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Reliable chip from 'unreliable' parts?

It sounds implausible, but European researchers are deadly serious about their aim to create reliable, low-energy microchips from what have traditionally been viewed as ‘unreliable’ components. The skill is to correct the errors to turn low-powered parts into efficient, reliable and, above-all, fault-tolerant chips. They propose to use nano-scale integration to build these next-generation chips.

Photo of an electronic chip
© Edelweiss fotolia

The main drivers of this research are quite simple: battery life and the environment. If the microprocessors in a smartphone, for example, use less power, then there is no need to recharge as often. And the positive spin-off of less charging is good for the environment.

Scientists in France, Ireland, the Netherlands, Romania and Serbia plan to develop new, low-powered – thus environmentally friendly – microchips to prolong the life of batteries used in the growing microelectronics market.

However, there is a back-story which needs to be told to understand the challenge they face. In 1965, Intel’s co-founder Gordon E. Moore predicted that overall processing power in computers would double every two years. His ‘law’ has more or less held sway ever since. But the smaller the chips become – and the more energy-saving components integrated into them (which save power and reduce heat) – the more unreliable they can become.

So the EU-funded Innovative reliable chip designs from low-powered unreliable components (i-RISC) project will investigate alternatives for producing high-quality chips that use tiny, nano-sized components that require much lower voltage, and thus use less power.

“The catch is that current technological processes in emerging nano-electronic devices make them inherently unreliable,” notes the project’s technical leader Valentin Savin of France’s Atomic Energy and Alternative Energies Commission (CEA).

As micro-devices become more ubiquitous – in everything from tablets to radio devices tracking products to sensors recording seismic changes – the key will be to increase processing power and decrease energy consumption without sacrificing reliability.

“Nano-scale, integrated chip-making using unreliable components is one of the most critical challenges facing next-generation electronic circuit design,” says Dr Savin.

From plausible to economic

Now, assuming it is plausible to overcome the complex technical requirements demanded of i-RISC, the next challenge the team then faces is to refine their results and scale up their processes to make such nano-scale integration economically viable.

“We believe a solution lies in the development of efficient and fault-tolerant data-processing and storage elements,” explains Dr Savin. The i-RISC project is working on innovative fault-tolerant solutions at both device- and system-level that are fundamentally rooted in mathematical models and algorithms (small programs). These draw heavily on information and coding theory – the fundamental building blocks of IT developments.

The researchers will combine the theories of George Boole – once a professor at University College Cork (Ireland) whose system of logic, or Boolean algebra, laid the foundations for digital computing – and Claude Shannon, the proclaimed “father of information theory”.

To do this, i-RISC will be looking to develop new methods for including error correction in the logical functionality of the circuit. “The error correction codec is like a wrapper that envelops the Boolean circuit,” explains Dr Savin.

While i-RISC cannot literally improve the materials, or at least their electronic properties –some materials like copper are better conductors than others which ‘leak’ information or charge – they can fix the problems resulting from using these materials.

Proposed solutions will build on what the team calls “fault-tolerant error correction” which consists of error-correcting codes and encoder/decoder architectures capable of providing reliable error protection even if they themselves operate on unreliable hardware.

The three-year project, which kicked off in February, will provide a first proof of concept by validating the proposed solutions on accurate error models and energy measurement tools developed within the research.

Nano-scale technologies are a paradigm shift in the way we perceive low-power, high-fidelity future microelectronics. “But nano-scale integration also requires a shift in the design paradigm combined with collaborative actions at all abstraction levels – from device up to processor and platform architecture. We are poised to provide the foundations for European industry to capture a lead in this emerging field,” suggests the i-RISC team.

 

Project details

  • Project acronym: I-RISC
  • Participants: France (Coordinator), Romania, Ireland, Serbia, Netherlands
  • Project FP7 309129
  • Total costs: € 2 161 095
  • EU contribution: € 1 613 284
  • Duration: February 2013 - January 2016

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