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This program aims at advancing the state-of-the-art in passive macromodeling and numerical simulation of electrical interconnects at chip, package, board and system level. Main objective is to ensure scalability and applicability to the more and more complex structures found in modern and expected in future technologies. The main results will be obtained by exploiting suitable techniques for model order reduction and compression, suitably combined with frequency-domain rational approximation methods, with the aim of extracting accurate behavioral models of moderate complexity. Whenever possible, the developed algorithms will be parallelized in order to take advantage of multicore high performance computing platforms, such as the IBM BladeCenter system available in the research lab
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