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Cristina Silvano

Cristina Silvano's picture
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Politecnico di Milano
Associate Professor

Cristina Silvano is an Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano. Cristina received her MS (Laurea) in Electrical Engineering from Politecnico di Milano in 1987.From 1987 to 1996, Cristina was Senior Design Engineer at the R&D Laboratories of Group Bull in Italy and Visiting Engineer at Bull R&D Labs, Billerica (MA - USA) (1988-89) and at IBM Somerset Design Center, Austin (TX - USA) (1993-1994). Cristina received her Ph.D. in Computer Engineering from the University of Brescia in 1999. Her primary research interests focus on computer architectures and electronic design automation, with particular emphasis on power-aware computing for embedded systems, design space exploration and runtime resource management for multi/many-core architectures and Network-on-Chip architectures. Her research has been funded by several national and international projects. Among them, Cristina was Project Coordinator of the European Project FP7-2PARMA-248716 on "PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures" (2010 - 2013). Previously, she was Project Coordinator of the European Project FP7-MULTICUBE-216693 on "Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications" (2008 - 2010). She has published over hundred peer-reviewed articles (including 14 IEEE/ACM Transactions and collecting one Best Paper Award) and she holds 11 international patents. Cristina serves in the program committee of several leading conferences in the computer architecture and design automation areas (including DAC, DATE, NOCS, FPL, HPCA, VLSI-SOC) and she was general co-chair of MICRO’08, general co-chair of SASP’09, program co-chair of  SASP’10 and program co-chair of  ASAP’12.


Blog posts

2PARMA Project: A Success Story

Disclaimer: this is a guest blog post. The authors are Prof. Cristina Silvano & Prof. William Fornaciari   

As our day-to-day expectations of technology increase so does the complexity of the processors required to meet those expectations. The current engineering approach is to increase the number of processing “cores”, individual compute engines, grouped inside a single processor chip.

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